Lead Ams Verification Engineer (Remote)

Position: Lead AMS Verification Engineer

Location: Remote

Duration: 1 Years

Job Description:

We are seeking highly skilled Lead AMS Verification Engineers to join our team. The ideal candidate will have extensive experience in AMS verification at both the SoC (chip) and block level, using netlist and/or models. This role requires a deep understanding of analog circuits, including low power circuits, PMIC, high-speed clocking circuits, and data converters. The candidate should also possess strong debugging skills and be proficient in AMS modeling using various languages.

Key Responsibilities:

Lead a project team of 3-5 AMS verification engineers

Create regular progress report of the project with updates from team members and share with project manager

Support project manager with technical inputs during meetings with customers

Technically front-end the team in interfacing with customer’s technical team.

Perform AMS verification at SoC and block levels using netlist and models.

Develop and maintain AMS models using Verilog, Verilog-A, Verilog-AMS, SystemVerilog, etc.

Understand and analyze the operation of analog circuits, including low power circuits, PMIC, high-speed clocking circuits, and data converters.

Debug and resolve issues in AMS verification processes.

Create and modify testbenches and test cases.

Implement checkers and assertions in UVM and SV environments.

Required Expertise:

6-8+ years of hands-on experience in AMS Verification, at least 2 years which is as a lead.

AMS verification at SoC (chip) and block level using netlist and/or models.

AMS modeling using Verilog, Verilog-A, Verilog-AMS, SystemVerilog, etc.

Strong understanding of analog circuits, including low power circuits, PMIC, high-speed clocking circuits, and data converters.

Excellent debugging skills.

Knowhow:

Proficiency in UVM and SV environments.

Experience with checkers and assertions.

Ability to create and modify testbenches and test cases.

Tool Exposure:

Cadence: AMS Designer with Spectre/Xcelium simulators.

Synopsys: VCS/VCS-XA Verilog AMS simulator.

Mentor: Symphony, AFS, Questa-sim.

Qualifications:

Bachelor’s, Master’s, or Ph.D. in Electrical Engineering.

, and HSPICE circuit simulation tools.

Knowledge of scripting languages (SHELL, PERL, SKILL), Excel macros, and MS Visio is a plus.

Rohit Chauhan